Using well known techniques, integrated circuits ("ICs") are fabricated on a wafer substrate by forming various depositions, layer by layer in a production facility that is often termed a "lab". For example, an IC containing metal-oxide-semiconductor ("MOS") devices has a thin layer of oxide over which a layer of conductive gate material (e.g., polysilicon) is formed and then defined. The MOS device source and drain regions are then formed, either by photolithography or by using the defined gates as a self-aligning mask. In some ICs, a capacitor may be formed by forming a layer of conductive material such as polysilicon over a thin layer of oxide. Normal backend processing completes the fabrication of the IC.
The IC is then functionally tested to detect and hopefully screen-out defective units. Understandably, defective units should not be packaged and delivered to customers.
In ICs containing MOS devices or IC capacitors, thin oxide (e.g., thin gate oxide or dielectric oxide) is a substantial factor contributing to IC failure. Two types of defective oxide are generally recognized in the art: weak oxide, and charge-damaged oxide.
Weak oxide is oxide that was formed inherently weak during fabrication, typically due to imperfections in the fabrication process. For example, the wafers may have been cleaned with contaminated wet chemicals, or contamination may be present in the gate oxide tube used during fabrication. In any event, such defects may exist randomly anywhere within the IC structure, and will affect the reliability of every structure formed on the wafer that utilizes thin oxide, e.g., every MOS device, and every capacitor.
By contrast, charge-damaged oxide is oxide that has been subjected to damage when the IC wafer was exposed to an environment with charged, energetic species. Such exposure can occur during such fabrication steps as plasma etching, plasma ashing, plasma deposition, ion implantation, and sputtering.
It is believed that the primary cause of charge-damaged oxide is charging of conductors overlying the oxide, typically due to plasma non-uniformities across the wafer surface. This non-uniformity produces electron currents and ion currents that do not balance locally. The resultant imbalance (e.g., net current flux to the wafer) appears to cause wafer surface charge, with increased voltage across the thin gate or capacitor oxide. The charging continues until the currents become balanced, or the thin oxide becomes damaged and begins to conduct, apparently via Fowler-Nordheim tunnelling.
If weak oxide formation could be identified, one might know to reexamine certain portions of the fabrication process, perhaps with respect to removing contamination from the wafer before oxidation. On the other hand, if charge-damaged oxide could be identified, one might know to reexamine the charge-producing portions of the fabrication process, perhaps with respect to generating a more uniform plasma field.
Unfortunately, prior art testing techniques cannot readily differentiate between an IC containing weak oxide and an IC containing charge-damaged oxide. Such testing is generally carried out using so-called antenna structures such as shown in FIG. 1.
In FIG. 1, at least in a preliminary state, an IC is formed on a wafer whose semiconductor substrate 10 that includes a layer of thin oxide 20 covered by a preferably polysilicon level 1 conducting region 30, as well as regions of thick field oxide 40. Whereas the thin oxide may be less than perhaps a few 100 .ANG. in thickness, the field oxide may exceed several thousand .ANG. in thickness. A relatively large conductive region 50, also preferably fabricated at the polysilicon 1 level, is formed atop the field oxide 40, and is coupled by a conductive segment 60, e.g., polysilicon, to the smaller conducting region 30 that overlies the thin oxide 20.
The formation of regions 30 and 50 produces two parallel-coupled capacitors C1 and C2 on a region of the IC wafer that is sufficiently large for implementation of capacitor C1. The "plates" of capacitor C1 are the large conductive region 50 and a region of the underlying substrate 10, which regions are separated by the thick field oxide 40. The "plates" of capacitor C2 are the smaller conductive region 30, and a region of the underlying substrate 10, which regions are separated by the thin oxide 20.
The area of conductive region 50 divided by the area of conductive region 30 defines a ratio (A.sub.R) for the antenna structure. Thus, if conductive region 30 has an area of perhaps 5 .mu.m.sup.2 and conductive region 50 has an area of 50 .mu.m.sup.2, the antenna ratio A.sub.R is 10; if conductive region 50 has an area of say 500,000 .mu.m.sup.2, A.sub.R is 100,000, and so on.
As shown in FIG. 1, the thin oxide dielectric layer of capacitor C2 is substantially thinner than the field oxide dielectric layer of capacitor C1. As a result, capacitor C2's "plates" are closer together. On one hand, because capacitance is inversely proportional to the separation between the capacitor "plates", capacitor C2 exhibits substantially greater capacitance per unit area than capacitor C1. However, total capacitance for a capacitor is proportional to plate area. Because the plate area ratios may well be in the range of several thousand or more, whereas the ratio between the thick field oxide and the thin oxide may be in the ten to one hundred range, the area effect will tend to dominate the plate separation or thickness effect.
Because the two capacitors are coupled in parallel, C1 and C2 see the same voltage. If a voltage V is induced across the capacitors, e.g., during plasma etching 100, the following equation governs: EQU Q1/C1=V=Q2/C2
Thus, any charge Q resulting from the plasma etching 100 will be shared such that substantially most of the charge will appear across the relatively large capacitance C1 (e.g., assuming that area effect dominates thickness effect), e.g., Q=Q1+Q2, where Q1&gt;&gt;Q2. As such, much of the plasma induced charge Q is collected by conductor region 50. However, any charge Q2 that exists over the thin oxide 20 covered by plate 30 will have the greatest impact due to the thinness of the oxide layer 20. Further, because leakage will occur through the thin oxide layer 20 and not through the thick field oxide 40, charge Q1 associated with capacitor C1 will be drained through capacitor C2 to the underlying substrate 10.
Shown generically in FIG. 1 are two types of oxide damage: weak oxide 110 (shown as circles) and charge-damaged oxide 120 (shown as triangles). These defects behave as if there were a resultant localized thinning of the oxide layer 20. Thus, while the defects are depicted as circles and triangles for ease of illustration, it is to be understood that these symbols do not literally represent the "shape", the "size", or the exact location of the defects.
Within the thin oxide layer 20, charge sharing can occur between regions of the layer having a nominal thickness and regions of the layer that are effectively thinner. The localized capacitance associated with the effectively thinner regions of layer 20 will be greater than the capacitance associated with the nominal thickness of layer 20. Thus, within the capacitor C2 defined over the thin oxide layer 20, there will be regions of higher capacitance associated with thinner regions of the oxide, per unit area. Charge distribution within capacitor C2 will tend to be maximized over the thinned oxide regions that include the defects 110, 120. As a result, the thinner, defect-containing, regions will tend to breakdown first relative to the nominally thick regions of thin oxide layer 20.
As suggested by FIG. 1, the weak oxide defects 110 can be found randomly and perhaps uniformly throughout the thin oxide layer. By contrast, the charge damage to the oxide will tend to occur beneath the conductive region 30, since any charge associated with capacitor C2 appears across a relatively thin oxide region. Any defects in the thick oxide 40 tend to be buried within and cannot appreciably thin or weaken the thick oxide.
Capacitors C1 and C2 may be formed using the same process steps carried out on the remainder of the IC wafer. For example, in subsequent process steps, an inter-layer dielectric may be formed over the polysilicon level 1 regions 30, 50, 60, (and other regions on the wafer). An overlying metal 1 region may then be added, followed by an inter-metal-oxide layer, and then perhaps an overlying metal 2 region, and so on. These additional process steps are not depicted in FIG. 1. However, many of these steps may involve charged energetic species, which can cause substantial charge to be collected in the conductive region 30. As noted, this charge can give rise to charge damage 120 in the underlying thin oxide 30. Because C1 and C2 are used only for testing, they need not be electrically coupled to the remainder of the IC.
Conventional antenna structures such as capacitors C1 and C2 are used in the prior art in an attempt to determine quality of thin oxide layer 20. At the simplest level, oxide testing can include coupling an over-voltage across the thin oxide, and measuring to determine whether any leakage current exceeds a predetermined threshold. For example, current exceeding say 1 nA may indicate either weak oxide, charge-damaged oxide, or both. Failed parts may be subjected to failure analysis to determine the root cause of failure.
Unfortunately, while leakage current measurements can identify a wafer containing weak oxide or charge-damaged oxide, prior art testing cannot readily discriminate between the two types of damage. A part evidencing excessive leakage current will be rejected using prior art techniques, even though the lot may still be usable if the leakage current resulted from charge-damaged rather than from weak oxide. Because it is not readily known whether weak oxide or charge-damaged oxide is at hand, one does not know whether to look for contamination in the fabrication process, or to re-examine the plasma-generating equipment.
It is also known in the art to test completed ICs using a so-called high temperature operation life ("HTOL") test that is performed at elevated temperature and perhaps over-voltage conditions. Industry accepted protocols for HTOL testing may be found in the "MIL.sub.-- STD.sub.-- 883C Handbook, Method 1005, Steady State Life". HTOL testing measures reliability of actual, completed IC products.
In HTOL testing, completed ICs on the wafer are packaged and then a sample, e.g., perhaps 1,000 parts, is tested to determine oxide reliability. Because what is HTOL-tested are finished parts, no antenna structures will be present. The sample ICs are first tested to ensure that they are functional. If so, the sample parts are mounted on dedicated printed circuit boards that are installed in an oven maintained at a higher temperature, perhaps 125.degree. C. The test parts are then electrically cycled by the application of operating power and test signals. Understandably at high temperature, the degradation mechanisms are accelerated, wherein the acceleration factor is known from prior experiments. To further accelerate testing, over-voltages are coupled to the parts, such that an IC containing 5 V devices will be tested at an operating level of perhaps 5.5 VDC, or higher.
The sample parts are tested for a fixed time, removed (or "pulled") from the oven, cooled, and then re-tested. Any part not passing the test is considered a failure and is removed from the sample, and perhaps subjected to failure analysis.
The remaining parts are subjected to further HTOL cycling. A typical sequence of "pull points" might be after 6, 24, 48, 96, 168, 500 and 1,000 hours of cumulative HTOL testing. At each pull point, about two days of manpower are required to test the parts. Typically, parts failing before 168 hours are termed "infant mortality", while parts surviving beyond 168 hours are used to calculate the expected failure rate in the field.
Unfortunately, prior art HTOL testing is an expensive and time consuming undertaking, as is any accompanying failure analysis. Typically the results of HTOL testing are not available for 2-3 months after the wafer was fabricated. Thus, prior art testing results in a significant delay before reliability information for a particular lot of wafers is available. In the interim, the fab that produced the sample lot may still be producing ICs with defective oxides, perhaps by using a contaminated diffusion tube or unbalanced plasma-generating equipment. Further, HTOL results are applicable primarily to the lot from which the samples were prepared. However defective oxide may vary from wafer to wafer, and from lot to lot. Thus, one lot tested for HTOL may have reliable oxide, whereas the next lot may not, or vice versa.
What is needed is a rapid and inexpensive way to test thin oxides, preferably at the wafer level before packaging. Such testing should require less than perhaps an hour per test lot, and should readily discern between weak oxide and charge-damaged oxide. Testing should be carried out using test structures and equipment that are not dedicated to the particular type of IC product being tested. Preferably, such test structures should be sufficiently small so as not to require substantial wafer area for implementation.
The present invention provides such a method and testing apparatus.